Semiconductor integrated circuit device and process for manufacturing the same

摘要

A large area dummy pattern DL is formed in a layer underneath a target T 2 region formed in a scribe region SR of a wafer. A small area dummy pattern in a lower layer and a small area dummy pattern Ds 2 in an upper layer are disposed in a region where the inter-pattern space of a pattern (active regions L 1 , L 2 , L 3 , gate electrode 17 ), which functions as an element of a product region PR and scribe region SR, is wide. The small area dummy pattern Ds 2 in the upper layer is offset by ½ pitch relative to the small area dummy pattern Ds in the lower layer.