发明名称 |
High speed power-gating technique for integrated circuit devices incorporating a sleep mode of operation |
摘要 |
A high speed power-gating technique for an integrated circuit device having a Sleep Mode of operation comprises providing an output stage coupled between a supply voltage source and a reference voltage source and driving a gate terminal of least one element of the output stage to a level above that of the supply voltage source or below that of the reference voltage source in the Sleep Mode of operation.
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申请公布号 |
US7359277(B2) |
申请公布日期 |
2008.04.15 |
申请号 |
US20040776101 |
申请日期 |
2004.02.11 |
申请人 |
UNITED MEMORIES, INC.;SONY CORPORATION |
发明人 |
HARDEE KIM C. |
分类号 |
G11C8/00;H01L21/822;G11C5/14;G11C7/10;H01L27/04;H03K5/153;H03K19/0948 |
主分类号 |
G11C8/00 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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