发明名称 DML DRIVER AND TRANSMISSION FRONT END
摘要 PROBLEM TO BE SOLVED: To generate a multiple value LD drive signal for PAM, high speed, with low power consumption, with a simple circuit configuration.SOLUTION: The DML driver includes a current sink circuit DRprovided for each bit k (k=0, 1, ..., n-1) of a digital input signal D. The current sink circuit DRcontrols sinking of a set current value Ipreset against the bit k from a constant current Isupplied to an LD in accordance with a bit value Dof the bid k.SELECTED DRAWING: Figure 2
申请公布号 JP2016122898(A) 申请公布日期 2016.07.07
申请号 JP20140260592 申请日期 2014.12.24
申请人 NIPPON TELEGR & TELEPH CORP <NTT> 发明人 KISHI TOSHIKI;HASE MUNEHIKO;NOSAKA HIDEYUKI;NOGAWA MASASHI;KIMURA SHUNJI
分类号 H04B10/516;H01S5/06 主分类号 H04B10/516
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