发明名称 |
PROCEDE DE MINIMISATION DE LA TENSION DE FONCTIONNEMENT D'UN POINT MEMOIRE DE TYPE SRAM |
摘要 |
An SRAM cell is formed of FDSOI-type NMOS and PMOS transistors. A doped well extends under the NMOS and PMOS transistors and is separated therefrom by an insulating layer. A bias voltage is applied to the doped well. The applied bias voltage is adjusted according to a state of the memory cell. For example, a temperature of the memory cell is sensed and the bias voltage adjusted as a function of the sensed temperature. The adjustment in the bias voltage is configured so that threshold voltages of the NMOS and PMOS transistors are substantially equal to n and p target threshold voltages, respectively. |
申请公布号 |
FR3024917(B1) |
申请公布日期 |
2016.09.09 |
申请号 |
FR20140057800 |
申请日期 |
2014.08.13 |
申请人 |
STMICROELECTRONICS SA;STMICROELECTRONICS INTERNATIONAL N.V. |
发明人 |
LECOCQ CHRISTOPHE;AKYEL KAYA CAN;CHHABRA AMIT;DIPTI DIBYA |
分类号 |
G11C11/405;G11C11/4074 |
主分类号 |
G11C11/405 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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