| 摘要 |
PURPOSE:To increase furthermore the in-phase component suppression ratio by inserting both the signal level shifting circuit and the clamping circuit between the output terminal of the emitter-follower circuit at the input stage and the input terminal of the emitter-coupled logic circuit. CONSTITUTION:Signal level shifting diode D1 plus signal clamping diodes D2 and D3 are inserted between the input terminal of the input-stage emitter-follower circuit to which pulses A and A' are supplied and the input terminal of the emitter-coupled logic circuit which is formed by giving an emitter coupling to transistors TR3 and TR4. Then resistances R2 and R3 are selected in order to secure Ec<Vref when the input terminal is opened as potential Ec at point C, the level of output terminal X becomes steady. The voltage drop is caused since pulse A passes through the area between the base and the emitter of TR1 as well as resistance R1. In this connection pulse A is connected to the base of TR3 via D1 to compensate the voltage drop amount of R1. At the same time, D2 is used in such way that the working of constant current source CC may not be impaired, and D3 clamps the input signals of TR3 and TR4 each. |
