发明名称 |
Double precision multiplier |
摘要 |
A double precision multiplyer for performing the multiplication of two double precision data using a 2's complement single precision multiplier. The 2n-1 bit double precision data is divided into one single precision data formed by taking the upper n bits of the double precision data and another single precision data formed by adding a "0" bit before the most significant bit of the remaining n-1 bits of the double precision data. Apparatus for performing the double precision multiplication thereby eliminates the necessity of discriminating the sign bit and enhances the speed of the double precision multiplication.
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申请公布号 |
US4722068(A) |
申请公布日期 |
1988.01.26 |
申请号 |
US19850727020 |
申请日期 |
1985.04.25 |
申请人 |
NEC CORPORATION |
发明人 |
KURODA, ICHIRO;NISHITANI, TAKAO;TANAKA, HIDEO;KAWAKAMI, YUICHI |
分类号 |
G06F7/533;G06F7/00;G06F7/52;G06F7/53;G06F7/76;(IPC1-7):G06F7/52 |
主分类号 |
G06F7/533 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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