| 摘要 |
Either the master address decode signal 4 generated by the master address decoder 3 or the reception interrupt factor vector decode signal 22 generated by the reception interrupt factor vector decoder 21 which decodes the reception interrupt factor vector 20, is select, ed by the decoder output select circuit 23 controlled by the interrupt vector register read signal 11, and the output from the decoder output select circuit 23 is given to each control register 5 as the multi function register select signal 24, and the AND signal of the multi function register select signal 24 obtained by the AND gate 110 and the interrupt vector register read signal 11, clears the interrupt request latch 6. During the time, by the interrupt vector register read signal 11, the bus cycle effective signal 9 to each control register 5 is masked.
|
