| 摘要 |
PROBLEM TO BE SOLVED: To generate the decoding clock of digital data element realizing excellent cost effect by using the crystal-stabilized self-running clock of comparatively high frequency generating a decoder by frequency division. SOLUTION: A reset pulse is transmitted to an RS-type flip-flop 662 through a terminal 64. The RS-type flip-flop 662 is set through a terminal 65 obtaining the data packet of a scanning line. A negative NAND operation gate 663 is made to operate as a switch through the output of the RS-type flip-flop 662. When the first bit of run in information is generated at the terminal 65, a pulse from a crystal oscillator 661 is sent to a frequency dividing circuit 664 through the NAND gate 663. The frequency dividing circuit 664 is set to be in a state defined through a logical circuit 665 controlled by the reset pulse of the terminal 64. The logical circuit 665 sets the logical level of the output 66 of the frequency dividing circuit 664 to be 'high' before a first run in bit appears. |
