| 摘要 |
PROBLEM TO BE SOLVED: To reduce power being consumed in a clock tree without increasing the layout area and internal power consumption. SOLUTION: A clock generating circuit generates a first clock signal and a second clock signal delayed behind the first clock signal. A switch circuit for transmitting an inputted logical value to the output, during an interval where the first clock signal has a high level and the second clock signal has a low level and during an interval where the first clock signal has a low level and the second clock signal has a high level, is disposed at the prestage of a logical value holding circuit in the flip-flop circuit. According to the arrangement, power consumption can be reduced without increasing the layout area. |
