| 摘要 |
A sub-word line driver in a semiconductor memory device is provided to reduce a power noise of a couple-cap NMOS(Negative Metal Oxide Semiconductor) transistor in the memory device by reducing the width of another NMOS transistor, which is connected to the couple-cap NMOS transistor. First NMOS transistors(M1) are gated by a source voltage. A normal word line enable signal is applied on a drain of the first NMOS transistor. Second NMOS transistors(M2) are series-connected to an upper side of the first NMOS transistors and gated by a voltage, which is generated at source terminals of the first NMOS transistor. Third NMOS transistors(M3) are gated by a second control signal, which is delayed from the first control signal, and series-connected to a lower side of the first NMOS transistors. Fourth NMOS transistors(M4) are gated by a third control signal, which is inverted from the first control signal, and series-connected to a lower side of the third NMOS transistors. Fifth NMOS transistors(M5) are gated by the source voltage and arranged at one side of the second NMOS transistors. A ground voltage terminal is formed at a lower side of the fourth NMOS transistors.
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