| 摘要 |
A majority voter circuit is provided to receive continuous n-bit data having first or second logic level, of which an output is changed depending upon the bit number of data having the same logic level. A first aligning unit(310) receives upper n/2-bit data among n-bit data, and relocates the same into data groups of first and second logic levels. A second aligning unit(320) receives low n/2-bit data among the n-bit data, and relocates the same into data groups of first and second logic levels. A third aligning unit(330) receives the data group of first or second logic level, and relocates the data into the data group of the first or second logic level. A voting unit(340) receives the lower n/2 bit data from the third aligning unit to vote majority of the first or second logic level.
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