| 摘要 |
The present invention relates to controlling the timing of a clock signal in high speed circuits, such as an analogue-digital converter (ADC). In some high speed data transfer techniques, the incoming data is latched using a clock signal. Often, the delay between the incoming data being clocked into the circuit and being ready to use (referred to as the "clock-to-Q period") is large enough to cause problems. In particular, the clock-to-Q period may be sufficient to result in the original clock signal being inappropriate to clock the latched signal. The present invention provides a data capture circuit with matched latch to address this issue, particularly a first latch having an input for receiving a data input signal; a first sense amplifier having an input coupled to an output of the first latch; a second latch having an input coupled to the output of the first sense amplifier and an output providing a first data output; and a clock generator, the clock generator comprising: a third latch having an input for receiving a first clock signal; a second sense amplifier having an input coupled to an output of said third latch; and a fourth latch having an input coupled to an output of said second sense amplifier and an output providing a first adjusted clock signal, wherein said first and third latches are substantially the same, the first and second sense amplifier are substantially the same and the second and fourth latches are substantially the same.
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