| 摘要 |
<p>The monitor, for a shift register counter, has two NAND-gate groups (D1-D5, D6-D10) - one for even and the other for odd numbers in the counter. The outputs of the two groups pass separately to two NAND-gates (D11, D12). These two latter NAND-gates are actuated and blocked by a flip flop (FF1) controlled by the input pulses to the counter. The outputs of these two NAND-gates are combined at a fifth NAND-gate (D13) which releases an alarm (S) when the counting procedure is faulty. The alarm is delayed, and the alarm circuit consists of a monoflop and two AND-gates.</p> |
