| 摘要 |
PURPOSE:To make it possible to maintain a fixed phase relation between write and read clocks by controlling an inhibiting circuit for read clocks by exercising a supervision over whether clocks are supplied to write and read counters. CONSTITUTION:Once input data and the 1st and 2nd clocks are applied to terminals 11, 12 and 13, write and read counters 19 and 20 start operating. When a phase difference between write clock WD and read clock RD exceeds a fixed value, inhibiting pulse generating circuit 30 supplies inhibiting pulse IH to FF31 and gates 37 and 32 inhibits the 2nd clock from passing through. While the 1st and 2nd clocks are supplied, clock OFF detecting circuits 33 and 34 send their outputs to eliminate the output of gate 36. The output of gate 36 is delayed 38 as long as the phase difference between clocks WD and RD reaches the fixed value and led to gate 37. Therefore, when clocks WD and RD bears the fixed phase relation, the phase control of circuit 30 is never performed unitl either the 1st or 2nd clock is interrupted. |
