| 摘要 |
PURPOSE:To reduce the number of multiplying circuits, by arranging in time-division within the unit computing time for both the real and imaginary number parts of a multiplicand. CONSTITUTION:The real number part (a) and the imaginary number part (b) of the multiplicant of the complex number supplied the input terminals 1 and 2 are arrayed in time division and within the unit arithmetic time (s) through a time dividing circuit 20 and with a timing T1. The output of the circuit 20 is supplied to the 1st and 2nd multiplying circuits 7 and 8 as a multiplicand respectively. While the real number part (c) and the imaginary number part (d) of the multiplier of the complex number supplied through input terminals 3 and 4 are supplied to the circuits 7 and 8 respectively. A multiplication is carried out between the parts (c) and (d) of the multiplicand and multiplier arrayed in time division through the circuits 7 and 8 to obtain products (e) and (f). These products (e) and (f) are delayed through delaying circuits 21 and 22 and by 1/2 unit computing time interval to deliver products e' and f'. A subtraction is carried out between e' and (f) through a subtracting circuit 11, and an addition is carried out through an adding circuit between (e) and f' to obtain a difference (g) and sum (h). Both (g) and (h) are latched by latching circuits 13 and 14 to obtain both the real and imaginary number parts of the product of a complex number. |
