| 摘要 |
PURPOSE:To elevate the reliability of a device which is equipped with an alternation memory, by comparing a parity which has been generated on the basis of an address to be applied to a main memory, and a read-out data, with a parity which has been stored in an alternation memory. CONSTITUTION:In case when an alternation memory 2 is not used as alternation of a main memory 1, a parity generator 6 generates a parity on the basis of an address ADD and a write data WD. This parity is stored in the memory 2 through a selector 10. Subsequently, a data which is read out from the memory 1, on the basis of the address ADD is inputted to a parity generator 7, and a parity is generated. Furthermore, on the basis of the address ADD, a parity is read out from the memory 2, too, and is outputted to a comparing circuit 5. The circuit 5 compares the parity which has been generated at the previous write time, with the parity which has been generated at the present read-out time. This comparison signifies checking whether the memory 2 is normal or not, and in the event of dissidence, it is informed by outputting, for instance, logical ''1'' from an output CD of the circuit 5. |
