发明名称 CLOCK REGENERATING CIRCUIT
摘要 PURPOSE:To realize a time division multiple access communication having very high line efficiency, by using phase difference information obtained from the past incoming burst as a regenerative clock of the burst incoming newly. CONSTITUTION:A band of a signal A including a clock component demodulated at a receiver is compressed 2, inputted to one input of a phase comparator 41 and an output of an oscillator 3 having a frequency very near this frequency is inputted to the other input of the comparator 41. This output signal F is transmitted to an AND gate 42, a signal difference from an output signal D of the oscillator 3 is given to an average circuit 5. This circuit 5 counts a phase difference pulse of a signal G for a period designated with a signal H of a control circuit 6, and the output is given to a storage circuit 7 as an average phase error information signal J. This circuit 7 stores average phase error information J in an address designated with a signal K with a write command signal M, is read out with a readout command signal L just before the incoming of the next burst signal, and applied to a phase shifting circuit 8 as regenerative clock phase information N.
申请公布号 JPS58204651(A) 申请公布日期 1983.11.29
申请号 JP19820087745 申请日期 1982.05.24
申请人 NIPPON DENKI KK;NIHON DENKI ENGINEERING KK 发明人 TAKAI HARUKI;MIURA MASAHIKO
分类号 H03L7/00;H04L7/00;H04L7/10 主分类号 H03L7/00
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