发明名称 |
Memory with improved write mode to read mode transition |
摘要 |
A memory has a read mode in which data is read from a bit line pair selected by a column address and a write mode in which data is written onto a selected bit line pair. The selected bit line pair is coupled to a data line pair via a column decoder in response to a column address. Upon a transition from the write mode to the read mode the column decoder is disabled from coupling the selected data line to the data line pair for the duration of a column disable pulse. The column disable pulse is generated in response to a write transition pulse or a column transition pulse or both. The column transition pulse is generated in response to a change in the column address. The write transition pulse is generated in response to a write to read transition.
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申请公布号 |
US4689771(A) |
申请公布日期 |
1987.08.25 |
申请号 |
US19860835679 |
申请日期 |
1986.03.03 |
申请人 |
MOTOROLA, INC. |
发明人 |
WANG, KARL L.;BADER, MARK D. |
分类号 |
G11C11/413;G11C7/10;G11C7/22;G11C11/41;(IPC1-7):G11C11/40 |
主分类号 |
G11C11/413 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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