| 摘要 |
A universal synchronizer for use in a variety of telecommunications systems based on direct digital phase synthesis (DDPS) include digital and analog PLLs. The synchronizer may be used for wireless, optical, or wireline transmission systems and for a wide ranges of data rates. Digital phase detectors are used in the digital PLLs for comparing the phase of the local clock fL with the phase of a respective digital reference clock, and provides a respective phase error signal. A digital phase synthesis unit receives the phase error signal and a target phase error and produces a first and a second set of control signals for driving an error driver. The error driver generates the control voltage for adjusting the frequency of a VCXO that is used for all PLLs, to lock the respective PLL. The first set of control signal generates the control voltage for the digital PLLs, and the second set of control signals generates the control voltage for the analog PLLs and for the acquisition mode of operation of all PLLs. The frequency and the width of the members of the first and second set of control signals are adjusted with a density width code, which is calculated for a target value and for the specific configuration of the synchronizer.
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