| 摘要 |
<p>Disclosed is an integrated circuit having a plurality of combinations of an integrated unit capacitor (C1) connected in series with a controlled channel of an integrated transistor switch (Q1). The series-connected capacitor and switch combinations (C1,Q1) are connected in parallel, and the switches (Q1) include a control gate coupled to a bit output of a register (14) via a control line. The capacitance of the variable capacitor depends on what word is stored in the register (14). Control gates for a different number of capacitor and switch combinations (C1,Q1) are connected to each bit output (16,18,...N), and the numbers are weighted using, for example, a binary weighting scheme. The variable capacitor is coupled to a balanced signal line pair (8,10), with capacitor and switch combinations (C1,Q1) comprising a switch connected between two capacitors that are connected to a line of the balanced signal line pair (8,10). Such arrangement is highly linear and even order distortion is reduced. The disclosed integrated circuit arrangements reduce the sensitivity to noise on the control line of the device. Variations in voltage applied to the control line and thus to the control gate of the switch vary the resistance value of the switch when closed, yet affect the value of the capacitive portion of the impedance very little. The disclosed capacitors are useful in circuits that need to be accurately trimmed once (for example, filters) and in circuits in which variable capacitance is required, such as voltage controlled oscillators (VCOs). <IMAGE></p> |
