发明名称 TESTING CIRCUIT AND TESTING METHOD FOR SEMICONDUCTOR DEVICE AND SEMICONDUCTOR CHIP
摘要 A testing circuit and a testing method for a semiconductor device and a semiconductor chip are provided to prevent decoding and modulating data of the chip, by cutting a test mode setting ROM and a test pad after testing the semiconductor device and using Manchester encoding signal synchronously with a dividing clock. In a testing circuit of a semiconductor device, a pad is formed on a diced region of a semiconductor wafer. A memory unit(6) is formed on the diced region, and stores a program for executing a test mode. A control circuit(5) is formed on a chip region of the semiconductor wafer, and decodes a logic signal input from the pad and sets a test mode by the program stored in the memory unit.
申请公布号 KR20070089561(A) 申请公布日期 2007.08.31
申请号 KR20060058959 申请日期 2006.06.28
申请人 FUJITSU LIMITED 发明人 SUGIYAMA HIDETOSHI;NAKAJIMA MASAO;MOURI HARUYUKI;SUZUKI HIDEAKI
分类号 G11C29/00;G01R31/28;H01L21/66;H01L21/822;H01L27/04 主分类号 G11C29/00
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