| 摘要 |
An integrated circuit thin film resistor structure includes a first dielectric layer ( 18 A) disposed on a semiconductor layer ( 16 ), a first dummy fill layer ( 9 A) disposed on the first dielectric layer ( 18 B), a second dielectric layer ( 18 C) disposed on the first dummy fill layer ( 9 A), the second dielectric layer ( 18 B) having a first planar surface ( 18 - 3 ), a first thin film resistor ( 2 ) disposed on the first planar surface ( 18 - 3 ) over the first dummy fill layer ( 9 A). A first metal interconnect layer ( 22 A,B) includes a first portion ( 22 A) contacting a first head portion of the thin film resistor ( 2 ). A third dielectric layer ( 21 ) is disposed on the thin film resistor ( 2 ) and the first metal interconnect layer ( 22 A,B). Preferably, the first thin film resistor ( 2 ) is symmetrically aligned with the first dummy fill layer ( 9 A). In the described embodiments, the first dummy fill layer is composed of metal (integrated circuit metallization).
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