Clock Signal Generation Device, Semiconductor Integrated Circuit, and Data Reproduction Method

摘要

The present invention improves a lead-in time of the PLL with a phase error detector having an enlarged range of phase error detection and gain control based on the PLL synchronous state. The phase error detection range is enlarged by correcting the phase error detection point in a case where the phase error increases. A locked state of the PLL is determined based on a standard deviation of the smoothed phase error values and the gains are switched between a lead-in transient state and a stationary state. As a result, it is possible to shorten and stabilize the lead-in time of the PLL.