HARDWARE ACCELERATOR FOR PACKET CLASSIFICATION

摘要

Systems and methods for packet classification hardware acceleration are provided. According to one embodiment, a packet classification hardware accelerator system includes multiple packet classification hardware units, a memory and a cache subsystem. The packet classification hardware units are each capable of operation in parallel on a corresponding decision tree of multiple decision trees that have been derived from respective subsets of a common ruleset defining packet classification rules based on header fields of packets. The memory has stored therein non-leaf nodes, leaf nodes and rules associated with the decision trees. The cache subsystem is coupled in communication with packet classification hardware units and the memory and has stored therein (i) a cached portion of the non-leaf nodes distributed among multiple non-leaf node caches, (ii) a cached set of the leaf nodes in a leaf node cache and (iii) a cached set of the rules.

主权项

1. A packet classification hardware accelerator system comprising:
a plurality of packet classification hardware units each capable of operation in parallel on a corresponding decision tree of a plurality of decision trees, wherein the plurality of decision trees are derived from respective subsets of a common ruleset defining packet classification rules based on header fields of packets; a memory having stored therein non-leaf nodes, leaf nodes and rules associated with the plurality of decision trees; and a cache subsystem, coupled in communication with the plurality of packet classification hardware units and the memory, having stored therein (i) a cached portion of the non-leaf nodes distributed among a plurality of non-leaf node caches, (ii) a cached set of the leaf nodes in a leaf node cache and (iii) a cached set of the rules.