Frequency divider for binary input signal - with pulse width equal to half the period

摘要

The output signal frequency is an integral fraction of that of the input signal. Input signal (E) and inverted signal (E1) are applied to the counters (Z1, Z2) which, starting from a lowest possible number (0), count upwards, and on reaching a specified number deliver output signals (S1, S2)a bistable flip-flop (F1) is tripped by the signals (S1, S2) into its "1" or "0" state. Its output is the divider output signal. It also delivers two blocking signals (R1, R2) resetting the corresponding counter to zero and holding it there until the next blocking signal appears.