| 摘要 |
PROBLEM TO BE SOLVED: To make improvement of noise immunity with respect to power supply voltage noise on the inside of a semiconductor integrated circuit or jitter of an external clock signal compatible with reduction in a phase synchronization lock time. SOLUTION: A phase of a reference clock signal CLK and a phase of an internal clock signal ICK are compared synchronously with a change in the reference clock signal CLK, a value of a delay section CNT is controlled to be changed corresponding to the polarity of a phase difference to control the phase of the internal clock signal ICK with respect to the reference clock signal CLK. In this case, number of times when the polarity of the phase difference is consecutively coincident is counted synchronously with a change in the reference clock signal CLK and till the count reaches a preset number of times, while the phase difference is in a lock range, the revision control of the delay control signal CNT is locked. |
