发明名称 CLOCK COMPENSATION DEVICE FOR SEMICONDUCTOR DEVICE
摘要 <p>PROBLEM TO BE SOLVED: To shorten the locking time and to secure an expanded frequency range by outputting a pump potential to perform the control so as to keep the phase difference within a range of delay of delay elements between the external and internal clocks if the phase difference gets out of the range of delay. SOLUTION: When the delay time is set at 2ns, for example, the delay times of outputs OUT0 to OUT3 of the 1st to 4th delay elements are set at 2ns, 4ns, 6ns and 8ns respectively. Then an external clock is inputted to a multiplexer as soon as it's inputted to a delay element. If the phase difference is set at 4ns between the external clock and an internal clock that is first outputted, the output OUT1 is selected via the multiplexer to delay the internal clock by 4ns. However, if the phase difference is smaller than 2ns or larger than 8ns between the internal and external clocks, a charge pump raises or drops its potential Vpump to totally control a range of delay.</p>
申请公布号 JPH11316620(A) 申请公布日期 1999.11.16
申请号 JP19980343634 申请日期 1998.11.18
申请人 HYUNDAI ELECTRONICS IND CO LTD 发明人 CHOI JAE MYOUNG
分类号 G06F1/10;G06F1/12;G11C11/407;G11C11/4076;H03K5/13;H03L7/081;H03L7/089;(IPC1-7):G06F1/10 主分类号 G06F1/10
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