发明名称 |
Parametric test system and method |
摘要 |
A system and method for reducing voltage stabilization time in a leakage current test system, and thereby reducing the time for measuring leakage currents in the I/O pins of an IC chip including CMOS DRAMs is disclosed. The method and system of the present invention accelerates leakage current testing time by precharging the capacitance of the I/O pins under test to a voltage near the settled voltage level, before measuring leakage current at the I/O pin contact points of packaged IC chips and assembled IC modules, and indicating when an I/O pin is defective.
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申请公布号 |
US6008664(A) |
申请公布日期 |
1999.12.28 |
申请号 |
US19980033285 |
申请日期 |
1998.03.02 |
申请人 |
TANISYS TECHNOLOGY, INC. |
发明人 |
JETT, ALLEN;LAWRENCE, ARCHER R. |
分类号 |
G01R19/00;(IPC1-7):G01R31/02;G01R31/26 |
主分类号 |
G01R19/00 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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