发明名称 |
Process for manufacturing a semiconductor material wafer having power regions dielectrically insulated from circuitry regions |
摘要 |
A manufacturing process is carried out starting from an SOI type wafer including a top silicon layer and a bottom silicon layer separated from each other by a buried silicon dioxide layer. In the top layer, a LOCOS type sacrificial region is formed and then removed, so as to form a cavity that extends in depth as far as the buried oxide layer. Subsequently, the cavity is filled with epitaxial or polycrystalline silicon, so as to form a power region extending between the top surface and the bottom surface of the wafer; then lateral insulation regions are formed that insulate the power region from the circuitry region.
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申请公布号 |
US6331470(B1) |
申请公布日期 |
2001.12.18 |
申请号 |
US20000580364 |
申请日期 |
2000.05.26 |
申请人 |
STMICROELECTRONICS S.R.L. |
发明人 |
SANFILIPPO DELFO;LEONARDI SALVATORE |
分类号 |
H01L21/762;(IPC1-7):H01L21/331 |
主分类号 |
H01L21/762 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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