发明名称 Memory protection system and method for computer architecture for broadband networks
摘要 A computer architecture and programming model for high speed processing over broadband networks are provided. The architecture employs a consistent modular structure, a common computing module and uniform software cells. The common computing module includes a control processor, a plurality of processing units, a plurality of local memories from which the processing units process programs, a direct memory access controller and a shared main memory. A synchronized system and method for the coordinated reading and writing of data to and from the shared main memory by the processing units also are provided. A hardware sandbox structure is provided for security against the corruption of data among the programs being processed by the processing units. The uniform software cells contain both data and applications and are structured for processing by any of the processors of the network. Each software cell is uniquely identified on the network. A system and method for creating a dedicated pipeline for processing streaming data also are provided.
申请公布号 KR100890134(B1) 申请公布日期 2009.03.20
申请号 KR20037012342 申请日期 2003.09.22
申请人 发明人
分类号 G06F12/14;(IPC1-7):G06F12/14 主分类号 G06F12/14
代理机构 代理人
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