APPARATUS FOR REDUCING JITTER IN A DESYNCHRONIZER

摘要

An apparatus, to be used in a desynchronizer, for minimizing the output jitter o f the desynchronizer. The desynchronizer is assumed to include a bit buffer for stagin g data that is to be output. The desynchronizer is also assumed to include a means for decoding the input signal to determine how justification opportunities in the input signa l are used and therefore what justification bits must be leaked by the desynchronizer. The apparatus and method of the present invention uses the information about the incoming just ification bits or incoming justification bytes and the state of the buffer to determine th e longest possible time to wait before issuing a command to momentarily speed up or delay outputting the next data unit from the bit buffer. This speeding up or delay is caused by sending a clock signal to the bit buffer that is shifted in phase by a small amo unt, thereby spreading out the effect of an incoming positive or negative justification bit o r byte over many periods of the output clock of the desynchronizer.