发明名称 |
SYSTEM AND METHOD FOR IMPLEMENTING AND VALIDATING STAR ROUTING FOR POWER CONNECTIONS AT CHIP LEVEL |
摘要 |
A system, method, and computer program product for automating the design and routing of non-shared one-to-many conductive pathways between a common pad and circuit blocks in an integrated circuit. Such pathways are routinely required for power and signal distribution purposes. Automated scripts perform a star routing methodology and validate the routing results. The methodology processes input width and layer constraints and from-to's denoting start and end points for each route by invoking a star_route command in a router that implements interconnections as specified. Routing results are validated by checking for routing violations, including shared segments and width violations. Violations are marked for correction. |
申请公布号 |
US2016210393(A1) |
申请公布日期 |
2016.07.21 |
申请号 |
US201514806462 |
申请日期 |
2015.07.22 |
申请人 |
CADENCE DESIGN SYSTEMS, INC. |
发明人 |
CHAVHAN Ankur;JAIN Devesh;FARHAT Behnam;FREIDLIN Andrey;SHANMUGAM Sundararajan;ZHANG Susan Zueqing |
分类号 |
G06F17/50 |
主分类号 |
G06F17/50 |
代理机构 |
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代理人 |
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主权项 |
1. A processor-implemented method for automatically creating multiple non-shared one-to-many routed conductive pathways in a circuit design, the method comprising:
using a processor:
for each intended conductive pathway:
creating constraints for the widths and conductive layers allowed for each pathway portion;specifying a from-to denoting a start point and an end point;invoking a computer-operated star router tool to route the intended conductive pathways according to the constraints and the from-to's; andtangibly outputting the routed conductive pathways. |
地址 |
San Jose CA US |