| 发明名称 |
MEMORY CHANNEL THAT SUPPORTS NEAR MEMORY AND FAR MEMORY ACCESS |
| 摘要 |
A semiconductor chip comprising memory controller circuitry having interface circuitry to couple to a memory channel. The memory controller includes first logic circuitry to implement a first memory channel protocol on the memory channel. The first memory channel protocol is specific to a first volatile system memory technology. The interface also includes second logic circuitry to implement a second memory channel protocol on the memory channel. The second memory channel protocol is specific to a second non volatile system memory technology. The second memory channel protocol is a transactional protocol |
| 申请公布号 |
US2016210251(A1) |
申请公布日期 |
2016.07.21 |
| 申请号 |
US201615081164 |
申请日期 |
2016.03.25 |
| 申请人 |
NALE Bill;RAMANUJAN Raj K.;SWAMINATHAN Muthukumar P.;THOMAS Tessil;POLEPEDDI Taarinya |
发明人 |
NALE Bill;RAMANUJAN Raj K.;SWAMINATHAN Muthukumar P.;THOMAS Tessil;POLEPEDDI Taarinya |
| 分类号 |
G06F13/16;G06F13/42;G06F13/40 |
主分类号 |
G06F13/16 |
| 代理机构 |
|
代理人 |
|
| 主权项 |
1. A semiconductor chip comprising:
memory controller circuitry having interface circuitry to couple to a memory channel, the memory controller circuitry including; first logic circuitry to implement a first memory channel protocol on the memory channel through the interface circuitry, said first memory channel protocol specific to a first volatile system memory technology; second logic circuitry to implement a second memory channel protocol on the memory channel through the interface circuitry, said second memory channel protocol specific to a second non volatile system memory technology, said second memory channel protocol being a transactional protocol. |
| 地址 |
Livermore CA US |
