| 摘要 |
PURPOSE:To prevent the generation of overrun and to cope with a wide range of working speeds from low to high levels, by controlling the clock frequency according to the value of a counter. CONSTITUTION:The data signal supplied from a data terminal 1 is converted at a reception part 6 and sent to a digital synchronizing network 3. The part 6 understands characters for each word of received data and then sends them to the network 3. The data received from the network 3 is converted by a transmission part 7 and sent to a data terminal 1. A word detecting circuit 8 detects the words of the received data and stores these words one by one to a word buffer 9. These words are delivered to the terminal 1 by the clock signal. The cycle of each bit is set equal to the clock cycle of the terminal 1. At the same time, a word counter 11 displays the number of stored words of the buffer 9. Thus it is possible to prevent the overflow of the buffer 9 by controlling the clock frequency while looking at the number of words. |
