发明名称 ERROR DETECTING SYSTEM
摘要 PURPOSE:To detect an error of an equal interval value generating circuit by a small hardware quantity by comparing those which should be equal to each other with regard to a surplus of 3 generated from an equal interval value, and a surplus of 3 generated from a head value and an interval value. CONSTITUTION:A head value and an interval value are inputted to equal interval generating circuits 1-6 through an input line 60 and through a data line, respectively. From these equal interval generating circuits 1-6, an equal interval value is outputted in order through data lines 71-76, and supplied to surplus generating circuits 11-16 of 3. That is to say, the head value and the interval value are denoted as X (integer) and Y (integer), respectively, and in the equal inteval value of X+iY (i=0, 1, 2...n) from X, Xmod3, [(Xmod3)+(Ymod3)]mod3, and [(Xmod3)+(2Ymod3)]mod3 are used as a surplus of 3 for an inspection, and compared with a surplus of 3 of 3X+iY in which a surplus of 3 of (i) becomes 0, 1 and 2 in order, in values to X+iY from X, by which an error is detected.
申请公布号 JPS60132248(A) 申请公布日期 1985.07.15
申请号 JP19830223489 申请日期 1983.11.28
申请人 NIPPON DENKI KK 发明人 KADAIRA GIZOU
分类号 G06F11/10;H03M13/09;(IPC1-7):G06F11/10 主分类号 G06F11/10
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