The circuit magnifies a desired portion of the picture of a television by linearly compensating the video signals in the horizontal and vertical directions. The circuit includes: a control logic circuit (43) for generating data selection control signals; a frame memory (44) for storing the data; a delaying circuit (46) for delaying the output of the frame memory (44); a first adder (47) for summing up the output of the delaying circuit (46); a first half value period generator (48) for dividing the output of the first adder into two halves; two AND gates for selecting the output of the first half value period generator; an OR gate for summing up the output of the AND gates; a clock delaying circuit (50) for delaying the output of the OR gate; a second adder (51); a second half value period generator (52); other AND gates and another OR gate.
