| 摘要 |
When the margin between a write frequency-divided clock signal and a read frequency-divided clock signal becomes remarkably decreased, a clock phase difference detecting circuit outputs a reset execution command. While a reset execution command is being output in a blanking interval, a reset signal generating circuit supplies a reset signal to an input side counter corresponding to a reset execution command so as to reset the phase of the write frequency-divided clock signal to an initial state.
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