| 摘要 |
The invention relates to a method for processing ATM cells in upstream and downstream bidirectional data flows in an ATM component in which the processing speed is greater than the mean cell rate and empty cycles without ATM cells are present in the cell flow. To allow for two-way alternate processing of upward and downward cells, the processing logic (VAL) of the component (BST) issues requests (EC up req, EC down req) for empty cycles upstream and downstream to an empty- cycle control unit (LZS) so as to obtain processing time. The cells of the downstream data flow can be stored and released separately in a buffer (BUF) so that in this way empty cycles can be generated downstream. Should an empty cycle occur, an upstream request for empty cycles (EC up req) is processed as a priority in relation to a simultaneous downstream request. In case of a downstream empty cycle request (EC down req) an empty cycle is released with a delay of one cycle period if there is a simultaneous upstream request. If this is not the case, it is released immediately. |
