Multi-channel time-interleaved analog-to-digital converter

摘要

The present invention provides a multi-channel time-interleaved analog-to-digital converter, including: a clock generation circuit, configured to generate a work clock of the analog-to-digital converter; a channel ADC group, including M ADC channels, and configured to convert, under the control of the clock generation circuit and in a time division multiplexing manner, one high-speed analog input signal into M low-speed digital output signals; a channel mismatch detection circuit, configured to detect in real time timing skew errors of output signals of the M ADC channels; a signal compensation and reconstruction circuit, configured to perform, according to the timing skew parameters detected, compensation and reconstruction on the digital output signals output by the channel ADC group; and a signal combining circuit, configured to combine the M low-speed output signals that are of the channels and generated after the compensation by the signal compensation and reconstruction circuit.

主权项

1. A multi-channel time-interleaved analog-to-digital converter (ADC), comprising:
a clock generation circuit, configured to generate a work clock of the analog-to-digital converter; a channel ADC group, comprising M ADC channels, arranged to be in a time-interleaved architecture, and configured to convert, under the control of the clock generation circuit and in a time division multiplexing manner, one high-speed analog input signal into M low-speed digital output signals, wherein M is an integer not less than 2, wherein sampling clocks of ADCs of adjacent subchannels in the M ADC channels have a phase difference of 2π/M; a channel mismatch detection circuit, configured to detect in real time timing skew errors of output signals of the M ADC channels, to obtain a timing skew parameter of each ADC channel relative to a reference ADC channel; a signal compensation and reconstruction circuit, configured to perform, according to the timing skew parameters detected by the channel mismatch detection circuit, compensation and reconstruction on the digital output signals output by the channel ADC group; and a signal combining circuit, configured to combine the M low-speed output signals that are of the channels and generated after the compensation by the signal compensation and reconstruction circuit, to obtain one final high-speed digital output signal.