发明名称 Semiconductor device and method of manufacturing the same
摘要 A semiconductor device in which misalignment does not cause short-circuiting and inter-wiring capacitance is decreased. Plural wirings are provided in a first interlayer insulating layer. An air gap is made between at least one pair of wirings in the layer. A second interlayer insulating layer lies over the wirings and first interlayer insulating layer. The first bottom face of the second interlayer insulating layer is exposed to the air gap. When a pair of adjacent wirings whose distance is shortest are first wirings, the upper ends of the first interlayer insulating layer between the first wirings are in contact with the first wirings' side faces. The first bottom face is below the first wirings' upper faces. b/a≦0.5 holds where a represents the distance between the first wirings and b represents the width of the portion of the first interlayer insulating layer in contact with the first bottom face.
申请公布号 US9379055(B2) 申请公布日期 2016.06.28
申请号 US201414490011 申请日期 2014.09.18
申请人 Renesas Electronics Corporation 发明人 Oshida Daisuke
分类号 H01L21/70;H01L23/522;H01L21/02;H01L23/488;H01L21/311;H01L23/532;H01L21/768;A61F13/34 主分类号 H01L21/70
代理机构 Foley & Lardner LLP 代理人 Foley & Lardner LLP
主权项 1. A method of manufacturing a semiconductor device comprising: forming a first interlayer insulating layer over a semiconductor substrate; making a plurality of wiring gutters in the first interlayer insulating layer and burying metal in the wiring gutters to form a plurality of wirings; etching back the first interlayer insulating layer using the wirings as a mask to form, between at least one pair of the wirings in the first interlayer insulating layer, a first trench having first side faces in contact with the wirings and a bottom face between the first side faces, wherein at least a portion of the first side faces is in direct contact with the wirings; anisotropically etching at least the bottom face of the first trench selectively to form a second trench in the first interlayer insulating layer; and forming a second interlayer insulating layer over the wirings and the first interlayer insulating layer and making an air gap between at least one pair of the wirings in the first interlayer insulating layer by infilling an upper portion of the second trench.
地址 Kanagawa JP