发明名称 Logic circuit and semiconductor device
摘要 The logic circuit includes an input terminal, an output terminal, a main logic circuit portion that is electrically connected to the input terminal and the output terminal, and a switching element electrically connected to the input terminal and the main logic circuit portion. Further, a first terminal of the switching element is electrically connected to the input terminal, a second terminal of the switching element is electrically connected to a gate of at least one transistor included in the main logic circuit portion, and the switching element is a transistor in which a leakage current in an off state per micrometer of channel width is lower than or equal to 1×10−17 A.
申请公布号 US9444459(B2) 申请公布日期 2016.09.13
申请号 US201213461282 申请日期 2012.05.01
申请人 Semiconductor Energy Laboratory Co., Ltd. 发明人 Sekine Yusuke
分类号 H03K19/20;H03K19/094;H03K19/00 主分类号 H03K19/20
代理机构 Fish & Richardson P.C. 代理人 Fish & Richardson P.C.
主权项 1. A logic circuit comprising: a first input terminal; a second input terminal; a first transistor comprising a first oxide semiconductor layer including a channel formation region; a second transistor comprising a second oxide semiconductor layer including a channel formation region, an output terminal; and a main logic circuit portion comprising a third transistor including a portion formed in a substrate including a semiconductor material, wherein one of a source and a drain of the first transistor is electrically connected to the first input terminal and the other of the source and the drain of the first transistor is electrically connected to the main logic circuit portion, wherein one of a source and a drain of the second transistor is electrically connected to the second input terminal and the other of the source and the drain of the second transistor is electrically connected to the main logic circuit portion, and wherein the main logic circuit portion is electrically connected to a first power supply potential line, a second power supply potential line, and the output terminal.
地址 Atsugi-shi, Kanagawa-ken JP