发明名称 Clocked pulse frequency modulation buck DC-to-DC converter
摘要 A hysteretic mode control circuit within a DC-to-DC converter is configured for varying the current limit that controls the switching interval and duration of a power switching section of the DC-to-DC converter to permit the DC-to-DC converter to manage large changes in output current load of the DC-to-DC converter. The hysteretic mode control circuit has a positive and a negative current limit section that develop a first and a second reference signal for turning on and turning off the first and the second switching device. The first and second reference signals are compared to an output voltage of the power switching section to determine if the first switching device or the second switching device is to be turned on or turned off.
申请公布号 US9444342(B2) 申请公布日期 2016.09.13
申请号 US201414516859 申请日期 2014.10.17
申请人 Dialog Semiconductor (UK) Limited 发明人 Childs Mark
分类号 H02M3/158;H02M3/155;H02M3/156;H02M1/00 主分类号 H02M3/158
代理机构 Saile Ackerman LLC 代理人 Saile Ackerman LLC ;Ackerman Stephen B.;Knowles Billy
主权项 1. A hysteretic mode control circuit within a DC-to-DC converter that is configured for operating in a continuous mode or a discontinuous mode, the hysteretic mode control circuit comprising: a first current limit circuit configured for determining a first reference limit signal that is used for controlling activation of a first switch of a switching section of the DC-to-DC converter for transferring current to a load device placed at an output of the DC-to-DC converter, wherein the first current limit circuit comprises: a first dynamic current limit circuit comprising: a first reference current source configured for providing a first maximum reference current;a first limit current mirror connected such that a reference leg of the first limit current mirror receives the first maximum reference current and configured such that a mirror leg of the first limit current mirror is connected to provide the first reference limit signal for an output of the first current limit circuit to determine the switching interval and duration of the first switch to provide a current to the filter section of the DC-to-DC converter;a comparator connected to receive the first reference limit signal and a feedback signal from the output of the DC-to-DC converter and configured for determining if the feedback signal is greater than or less than the first reference limit signal to generate an output signal; anda comparison switching device connected to receive the output signal of the comparator that is activated or deactivated to divert a current from the reference leg of the first limit current mirror and thus modify the current in the reference leg and thus the mirror leg of the first limit current mirror and thus adjust the voltage level of the first reference limit signal; and a pulse width modulation/pulse frequency modulation control circuit configured for receiving the first reference limit signal, configured for comparing an amplitude of the first reference limit signal with a feedback signal from a power switching section of the DC-to-DC converter and configured for generating a first reset control signal and a second reset control signal for controlling deactivation of the first switch and a second switch of the DC-to-DC converter; wherein the first current limit circuit and the pulse width modulation/pulse frequency modulation control circuit are configured for varying a current limit that controls an interval and duration of time at which the switching section of the DC-to-DC converter is switched to permit the DC-to-DC converter to manage large changes in an output current load of the DC-to-DC converter while operating in the discontinuous operation mode.
地址 Reading GB