| 摘要 |
PURPOSE:To fine bit line patterns by each extending gate electrodes in select transistors of several row in the direction orthogonal to the direction that bit lines extend and connecting the gate electrodes to gate electrodes in select transistors of adjacent rows in common. CONSTITUTION:A plurality of word lines WL and a plurality of bit lines BL are mutually crossed at right angles and arranged in a memory cell region 1, and memory cells MC are mounted severally where each work line WL and each bit line BL cross. Separate word line WL is connected to a row decoder circuit 2. Several bit line BL is connected to bit line select transistors QB. The bit line select transistors QB are divided into four blocks 31, 32, 33, 34 and column select signals B1, B2...B8 are each applied to gates in the bit line select transistors QB of separate block from a first column decoder circuit 4. The bit lines BL from the bit line transistors QB of several block are connected in common at every block, and each connected to a sense amplifier circuit SA through block select transistors QA.
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