| 摘要 |
PURPOSE:To attain the detection/protection of a synchronizing signal without malfunction by controlling a counter counting a master clock based on a signal which is formed by synchronizing a recovered clock from an intermittent reproduced PCM output and the master clock in a prescribed timing at a synchronizing circuit. CONSTITUTION:When a synchronizing signal detection circuit 31 detects a synchronizing signal DSYNC from an intermittent reproduced PCM signal, so long as the signal DSYNC is within the window period through the detection of a window counter 36 or the like, a flag processing circuit 35 outputs a control synchronizing signal BSYNC to control a word counter 34 and a bit counter 33 counting a recovered clock. On the other hand, in receiving the signal BSYNC, a synchronizing circuit 32 synchronizes the recovered clock and the master clock to output a signal CSYNC, a protection counter 38 and the counter 36 counting the master clock via the circuit 35 are controlled based on the signal BSYNC to prevent the generation of asynchronous error by the counters 33, 34 and 36, 38 counting an asynchronizing clock. As a result, the detection/ protection of synchronization without malfunction is attained.
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