| 摘要 |
PURPOSE:To improve the verification efficiency by generating stored contents of a memory circuit at the same timing as storage of operation information of the memory circuit or outputting a clock or simulation data generated in a data processing control part to perform simulation. CONSTITUTION:Operation information of an information processor 9 as the object to be analyzed is taken into the memory circuit 6. This taken-in information of the memory circuit 6 is generated at the same timing as operation information taking-in by a simulation data output control part 11 and is outputted back to the information processor 9 through an information processor I/F part 10. Then, this processor is operated as a simulated information processor. Contents of the memory circuit 6 are changed for the timing or the operation different from that of the information processor as the object to be analyzed by setting from an operation key 8 and are outputted through the information processor I/F part 10 and the simulation data output control part 11. Thus, an abnormal processing or the like different from the normal operation of the information processor 9 is easily simulated and tested. |
