| 摘要 |
Data after shifting is outputted from a output bus 9 by that, n-bit, data inputted to a input bus 1 is connected either to a first bus 3 or to a second bus 4, or to the both of them by a bus switching circuit 2, data either on the first bus 3 or the second bus 4 which is not connected to the bus switching circuit 2 is compensated by data compensating circuits 51, 52, a signal including a shift quantity and shift direction given from a shift quantity bus 6 is decoded by a decoder 7, and by performing plural-bit shifting by a MOS transistor array 8 of n numbers of line and n+1 numbers of column. Respective processings of logical shift, arithmetic shift and rotation are performed in both right and left directions by a single circuit configuration.
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