| 摘要 |
<p>A method of extracting timing characteristics from transistor circuit data of design assets (modules) of parts such as CPU core, wherein the extracted timing characteristics are used for timing constraints in performing the timing verification, logic synthesizing or timing-driven layout of a circuit including a module to be extracted, and, when the timing verification is to be performed by simulation, in particular, the verification without a pseudo eror can be made because the timing characteristics includes a timing rule conforming conditions of the module; a structure of a timing characteristic library; a storage medium storing the library; and an LSI designing method using the same.</p> |
