| 摘要 |
PURPOSE:To further speed up a data processing by executing the read-out operation of data from a memory and the write-in operation of the data to the memory exclusively for plural pipeline stages. CONSTITUTION:Data transfer between latch circuits 28 to 32 is controlled by communication between transfer control circuits 33 to 37. In a read-out pipeline stage 56, a read-out circuit 40 extracts an address for read-out to a memory 32 from the data of the latch 29, and the data of a processing pipeline stage 57 is logically operated, and the address for write-in to the memory 38 and the result of arithmetic operation among the latch data of a write-in pipeline stage 58 are extracted by a write-in circuit 42, and outputted to the memory 38. Then, the result of the arithmetic operation is stored in the memory 38. At this time, the operation of the read-out pipeline stage 56 is inhibited by a memory control circuit 51, and the write-in operation to the memory 38 is allowed to be executed in the write-in pipeline stage 58. |
