| 摘要 |
PURPOSE:To reduce the synchronization lock time at reception, to minimize sensitive phase correction at transmission and to improve the reliability by switching a synchronization protection stage number automatically without fixing the synchronization protection stage number to correct the title circuit. CONSTITUTION:A phase lead detection signal Sphi1 or a phase lag detection signal Sphi2 are inputted to a synchronization protection/control means 12. A synchronization protection control signal Ci representing number of synchronization protection stages is selected based on a phase of a signal RXD and a phase of a synchronization extraction clock Ci at the reception of the signal. An internal control signal CR based thereon is outputted to a frequency divider means 13. Moreover, when the signal RXD from a reception communication line L1 is processed by a reception means 14 at the transmission of a signal, the signal phi2 from a phase locked loop means 15 is subject to extraction processing by a control means 17. Thus, a transmission signal OXD based on the signal phi2 is outputted to a transmission communication line L2 from the transmission means 16 via the control means 17. |
