发明名称 MANUFACTURE OF SEMICONDUCTOR DEVICE
摘要 PROBLEM TO BE SOLVED: To prevent the formation of voids in a copper film filled in the recess of a high aspect ratio formed by an electrolytic plating method. SOLUTION: After a metal wiring 12 of a first layer is formed on an interlayer insulation film 11 of the first layer deposited on a semiconductor wafer 10, an interlayer insulation film 13 of a second layer is deposited on the film 11 of the first layer. After a contact hole 14 and a wiring groove 15 are formed in the film 13 of the second layer, a barrier layer 16 made of TaN is formed. After a seed layer 17, made of copper and having a width of about 10 nm, is formed by a sputtering method, an electroless copper plating is performed on the layer 17 to form a continuously reinforced seed layer 17A. After the reinforced seed layer is subjected to an electroless copper plating to fill the contact hole 14 and the inside of the wiring groove 15 with copper, a copper film exposed to the interlayer insulating film of the second layer is removed to form an embedded wiring having a dual-damascene structure.
申请公布号 JP2000183160(A) 申请公布日期 2000.06.30
申请号 JP19980352638 申请日期 1998.12.11
申请人 MATSUSHITA ELECTRIC IND CO LTD 发明人 HASHIMOTO SHIN
分类号 H01L21/3205;C23C18/31;C25D7/12;H01L21/288;H01L21/768;H01L23/52;(IPC1-7):H01L21/768;H01L21/320 主分类号 H01L21/3205
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